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All Papers | Key Papers by Topic
SCAMP Vision Chips
P.Dudek, “SCAMP-3: A Vision Chip with SIMD Current-mode Analogue Processor Array”, in “Focal-Plane Sensor-Processor Chips”, A.Zarandy (Ed.), ISBN: 978-1-4419-6474-8, p.17-43, Springer, 2011
P.Dudek and S.J.Carey, "A General-Purpose 128x128 SIMD Processor Array with Integrated Image Sensor", Electronics Letters, vol.42, no.12, pp.678-679, June 2006
P.Dudek and P.J.Hicks, "A General-Purpose Processor-per-Pixel Analog SIMD Vision Chip", in IEEE Transactions on Circuits and Systems - I, vol. 52, no. 1, pp. 13-20, January 2005
P.Dudek and P.J.Hicks, "A CMOS General-Purpose Sampled-Data Analogue Processing Element", in IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 47, no. 5, pp. 467-473, May 2000
ASPA / ACLA / Cellular Processor Arrays
A.Lopich and P.Dudek, "A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities", IEEE Transactions on Circuits and Systems - I, , vol 58, issue 10, pp. 2420-2431, October 2011
P.Dudek, "An Asynchronous Cellular Logic Network for Trigger-Wave Image Processing on Fine-Grain Massively Parallel Arrays", IEEE Transactions on Circuits and Systems - II, vol. 53, no.5, pp. 354-358, May 2006
A.Lopich and P.Dudek, “Asynchronous Cellular Logic Network as a Co-Processor for a General-Purpose Massively Parallel Array", International Journal of Circuit Theory and Applications, Volume 39, Issue 9, pages 963–972, September 2011
3D Chips
P.Dudek, A.Lopich and V.Gruev, “A pixel-parallel cellular processor array in a stacked three-layer 3D silicon-on-insulator technology”, European Conference on Circuit Theory and Design, ECCTD 2009, pp.193-197, August 2009
APRON
D.R.W.Barr and P.Dudek, "APRON: A Cellular Processor Array Simulation and Hardware Design Tool”, EURASIP Journal on Advances in Signal Processing, Article ID 751687, 9 pages, 2009
Neuromorphic Circuits / Neural Computation
J.H.B.Wijekoon and P.Dudek, "VLSI circuits implementing computational models of neocortical circuits", Journal of Neuroscience Methods, (in press)
J.H.B.Wijekoon and P.Dudek, "Compact Silicon Neuron Circuit with Spiking and Bursting Behaviour", Neural Networks, Vol 21, Number 2-3, pp 524-534, March/April 2008
J.H.B.Wijekoon and P.Dudek,"Analogue CMOS Circuit Implementation of a Dopamine Modulated Synapse", IEEE International Symposium on Circuits and Systems, ISCAS 2011, Rio de Janeiro, May 2011
K.Brohan, K.Gurney and P.Dudek, "Using reinforcement learning to guide the development of self-organised feature maps for visual orienting", Artificial Neural Networks - ICANN 2010, Lecture Notes in Computer Science, Volume 6353/2010, pp.180-189, September 2010
Image Processing
P.Dudek and D.L.Vilarino, “A Cellular Active Contours Algorithm Based on Region Evolution”, IEEE International Workshop on Cellular Neural Networks and their Applications, CNNA 2006, pp.269-274, Istanbul, August 2006
M.Geese and P.Dudek, "Autonomous Long Distance Transfer on SIMD Cellular Processor Arrays", IEEE Workshop on Cellular Nanoscale Networks and Applications, CNNA 2010, Berkeley, pp. 365-370, February 2010
S.Razmjooei and P.Dudek, "Approximating Euclidean Distance Transform with Simple Operations in Cellular Processor Arrays", IEEE Workshop on Cellular Nanoscale Networks and Applications, CNNA 2010, Berkeley, pp. 181-185, February 2010
C.Alonso-Montes, D.L.Vilariño, P. Dudek and M.G.Penedo, "Fast Retinal Vessel Tree Extraction: A Pixel Parallel Approach", International Journal of Circuit Theory and Applications, vol 36, issue 5-6, pp.641-651, July-September 2008
A.Lopich and P.Dudek, Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing, Journal of Signal Processing Systems, Springer, Volume 56, Number 1, pp. 91-103, July 2009
Chaos Oscillators
V.D.Juncu, M.Rafiei-Naeini and P.Dudek , "Integrated circuit implementation of a compact discrete-time chaos generator", Analogue Integrated Circuits and Signal Processing, Vol.46, Issue 3, pp. 275-280, March 2006
P.Dudek and V.D.Juncu, "Compact Discrete-Time Chaos Generator Circuit", Electronics Letters, Vol.39, No. 20, pp. 1431-1432, October 2003
Time to Digital Converter
P. Dudek, S. Szczepanski and J.V. Hatfield, "A High-Resolution CMOS Time to Digital Converter Utilising a Vernier Delay Line", in IEEE Journal of Solid State Circuits, vol.35, no.2, pp. 240- 247, February 2000
