Vision Chips
with Pixel-Parallel Cellular Array Processors
NEW - some results (including movies) of the SCAMP-3 chip can be found following this link
VISION CHIPS integrate image sensing and processing on a single silicon die. In a way somewhat resembling the vertebrate retina, these semiconductor chips perform preliminary image processing directly on the focal plane. They can provide high-performance, low power solution for computer vision applications in areas such as autonomous vehicle guidance, industrial inspection, robotics, surveillance, smart toys, etc
MASSIVELY PARALLEL PROCESSOR ARRAY: Low level image processing tasks are inherently pixel-parallel in nature, identical operations are performed on every image element (pixel). Integrating a processing element within each pixel of the image sensor array results in a massively parallel cellular array processor, capable of providing computational power required for real-time image processing. At the same time, this integration eliminates the I/O bottleneck between the sensor and the processor and dramatically reduces the power dissipation, size and cost of the system. The processor array operates in SIMD (Single Instruction Multiple Data) mode. Processing elements simultaneously execute identical instructions on their local data. The processors can also exchange information with their nearest neighbours. Each processing element, is a simple, but complete processor, comprising Arithmetic Logic Unit, Memory, Local Control and I/O ports and also include a photodetector.
SCAMP-3: In a high-resolution pixel-parallel SIMD vision chip the silicon area available for each processing element is very limited. Our key idea is the introduction of an analogue processing element (APE). The APE executes software instructions in a manner akin to a digital processor, but it operates on analogue samples of data. Compact registers are build using switched-current storage cells, arithmetic operations are performed without any extra hardware: adder circuit is replaced by current summation on the bus wire (Kirchhoff’s law). This combination of analogue circuitry and digital architecture results in unprecedented efficiency in terms of performance, cost and power dissipation. The SCAMP-3 chip, fabricated in a 0.35 um CMOS technology contains a 128x128 processor array and achieves cell density of 410 processors/mm2 (a single cell measures under 50um x 50um). Operating with a 1.25 MHz clock the maximum power consumption is 12 uW/cell. The computational power efficiency is 104 GOPS/W.
SCAMP-3 Evaluation/Development Kit: Enables the development of image processing algorithms and evaluation of the SCAMP-3 vision chip performance in custom applications. Provides all control and interface circuits for the vision chip, with a USB 2.0 based interface for development and parallel interface for custom hardware. The software includes Simulator/Development Environment, Graphical User Interface and Windows and Linix versions of Software Framework for custom applications.
ACKNOWLEDGEMENT: This research has been funded by the EPSRC
More results (including movies)
Dr Piotr Dudek, School of Electrical and Electronic Engineering, The University of Manchester, PO Box 88, Manchester M60 1QD, UK, Email: p.dudek@manchester.ac.uk