I am a PhD candidate in the School of Computer Science at The University of Manchester under the advisement of Dr Dirk Koch. I work primarily on resource management and virtualization for FPGAs. In particular, my PhD is focused on how we can dynamically scale up or scale out hardware accelerators at runtime without the user realizing. Which I like to call "resource elastic FPGA systems". It would allow users to deploy their hardware accelerators written in OpenCL/C to the cloud or edge with ease and high performance.
My CV can be found here.
Words I like to live by:
People of accomplishment rarely sat back and let things happen to them. They went out and happened to things. - Leonardo da Vinci
Teaching assistantCurrently, I am also a teaching assistant and proivde support for labs, marking and teaching (in labs).
PhD in Computer Science
At The University of Manchester, on Resource Management & FPGA Virtualisation for Cloud Computing as a President's Doctoral Scholar.Sep 2017 - Current
HTV - Consulting Embedded Platform Engineer
Developed an embedded platform with remote-access for cryptography acceleration on FPGAs.Sept 2018 - Nov 2018
BEng (Hons) Computer Systems Engineering
At Univesity of Manchester with specialisation in Computer Architecture and System on Chip. Final year thesis can be found here.Sept 2014 - July 2017
ARM - Hardware Intern - Design and Verification
Part of Verification IP team working on AMBA protocols (CHI, ACE, AXI) and its future variants.July 2016 - Sept 2016
Summer Research Assistant
Worked on Transport triggered and Dataflow Computer Architecture under Dr. Javier Navaridas.July 2015 - Aug 2015
- [Accepted/In-press] A. Vaishnav, K.D. Pham, K. Manev and D. Koch, "The FOS (FPGA Operating System) Demo", 29th FPL, Barcelona, 2019.
- A. Vaishnav, K.D. Pham and D. Koch, "Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures", 10th HEART, Nagasaki, 2019. Read Online
- K. Manev, A. Vaishnav, C. Kritikakis and D. Koch, "Scalable Filtering Modules for Database Acceleration on FPGAs", 10th HEART, Nagasaki, 2019. Read Online
- A. Vaishnav, K.D. Pham and D. Koch, "Live Migration for OpenCL FPGA Accelerators", FPT, Naha, 2018. (Best Paper Nominee) Read Online
- K.D. Pham, A. Vaishnav, M. Vesper, D. Koch, "ZUCL: A ZYNQ UltraScale+ Framework for OpenCL HLS Applications", 5th FSP, 2018. Read Online
- K.D. Pham, E. Horta, D. Koch, A. Vaishnav, T. Kuhn, "IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs", 12th MCSoC, 2018. Read Online
- A. Vaishnav, K.D. Pham, D. Koch and J. Garside, "Resource Elastic Virtualization for FPGAs using OpenCL", 28th FPL, Dublin, 2018. Read Online
- A. Vaishnav, K.D. Pham and D. Koch, "A Survey on FPGA Virtualization", 28th FPL, Dublin, 2018. Read Online
- A. Vaishnav, J. R. G. Ordaz and D. Koch, "A Security Library for FPGA Interlays", 27th FPL, Ghent, 2017. Read Online
- Full list can be found on Google Scholar.
Honours and Awards
- Given to the second-place winner of best research paper of the year across the school, based on the external reviews, venue and acceptance rate. For "Live Migration for OpenCL FPGA Accelerators".
- Given to top 3% of research students who demonstrate academic excellence and leadership potential, university-wide.
- This prize is awarded to the student who has, in the opinion of the Examiners, performed with distinction throughout their degree programme in examinations, laboratories and projects relating to Computer Engineering.
- For the sterling performance of the team throughout the year in all coursework and challenges of Software Engineering.
- Awarded on the grounds of academic merit to a student who has shown commitment, determination, enthusiasm, personal application and promise.
- For Excellence in first year studies in academic year 2014-15. Given to top 5 students of the year.
- Member of Organising Committee for Postgraduate Summer Research Showcase 2018.
In 2017 we had just over 160 posters on display from across the three faculties, a research image gallery, research films and 12 interactive posters on show.